Efficient Fault Coverage Vlsi Architecture for Lfsr Based Image Watermarking Sram

Recent advances in the development of image watermarking algorithms had made a rapid change in the authenticated information resource sharing. Among all techniques of image watermarking and storing watermarked image bits in SRAM (Static Random Access Memory), LFSR (Linear Feedback Shift Register) based image watermarking technique has been proposed in [1], this technique utilizes less design complexity for VLSI (Very Large Scale Integration ) on-chip hardware architecture compared with the other techniques. In our paper, the FPGA (Field Programmable Gate Array) prototyping of image watermarking SRAM [1] has been presented. In our paper, we are presenting BIST-R (Build in Self Test and Repair) based efficient fault coverage VLSI architecture, where the proposed method of SRAM hardware architecture can be utilized in real time image watermarking encoder and decoder applications. In our paper, LFSR based image watermarking SRAM build in self test and repair method has been presented. The comparative results have shown efficient fault coverage in detecting the faults in less time and utilized less power during the SRAM hardware implementation. We simulated and synthesized all our proposed modules using Xilinx 9.1i and ModelSim XE III 6.4b. The layout and sketch design of our modules for MBIST (Memory Build in Self Test) and MBISR (Memory Build in Self Repair) were implemented using layout and SPICE tools. The complete layout of our proposed method has been implemented on CMOS 0.12μm technology VSLI architecture.